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august 2008 rev 8 1/34 1 M41ST84W 3.0/3.3 v i 2 c serial rtc with 44 bytes of nvram and supervisory functions features automatic battery switchover and deselect ? power-fail deselect, v pfd = 2.60 v (nom) ?switchover, v so = 2.50 v (nom) 400 khz i 2 c serial interface 3.0/3.3 v operating voltage ?v cc = 2.7 to 3.6 v ultra-low battery supply current of 500 na (max) rohs compliance lead-free components are compliant with the rohs directive serial rtc features 400 khz i 2 c 44 bytes of general purpose nvram counters for: ? seconds, minutes, hours, day, date, month, and year ?century ? 10ths/100ths of seconds ? clock calibration register allows compensation for crystal variations over temperature programmable alarm with interrupt ? functions during battery backup mode power-down timestamp (ht bit) 2.5 to 5.5 v oscillato r operating voltage 32 khz oscillator wit h integrated load capacitance (12.5 pf) battery low flag microprocessor supervisory features programmable watchdog timer ? 62.5 ms to 128 s time-out period power-on reset/low voltage detect output pfi/pfo with 1.25 v reference other features programmable squarewave generator (1 hz to 32 khz) ?40c to +85c operation packaged in a 16-lead soic 16 1 so16 (mq) www.st.com
contents M41ST84W 2/34 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 timekeeper ? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 reset input (rstin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9 power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 t rec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M41ST84W contents 3/34 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of tables M41ST84W 4/34 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. timekeeper ? register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. t rec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15. so16 ? 16-lead plastic small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . 31 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M41ST84W list of figures 5/34 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. 16-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 8. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16. rstin timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17. ac testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19. so16 ? 16-lead plastic small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
description M41ST84W 6/34 1 description the M41ST84W serial real-time clock is built in a low power cmos sram process. it has a 64-byte memory space with 44 bytes of nvram and 20 memory-mapped rtc registers (see table 3 on page 18 ). the rtc registers are configured in binary coded decimal (bcd) format. a built-in, low power 32.768 khz oscillator (ext ernal crystal controlled) provides the time base for the timekeeping and calendar functions. the basic clock/calendar functions are handled by the first eight rtc registers, while the other twelve bytes provide status/control for the alarm, watchdog, and square wave functions. addresses and data are transferred serially via the two line, bidirectional i 2 c interface. the built-in address register is incremented automat ically after each write or read data byte. the M41ST84W has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. the energy needed to sustain the sram and clock operations can be supplied by a small lithium button- cell supply when a power failure occurs. functions available to the user include a non- volatile, time-of-day clock/calendar, alarm interrupts, watchdog timer and programmable square wave output. other features include a power-on reset as well as an additional input (rstin ) which can also generate an output reset (rst ). the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the M41ST84W is supplied in a 16-lead soic package.
M41ST84W description 7/34 figure 1. logic diagram table 1. signal names xi oscillator input xo oscillator output irq /ft/out interrupt/frequency te st/out output (open drain) pfi power fail input pfo power fail output rst reset output (open drain) rstin reset input scl serial clock input sda serial data input/output sqw square wave output wdi watchdog input v cc supply voltage v bat battery supply voltage v ss ground nc no connect ai03677 scl v cc M41ST84W v ss sda rstin irq/ft/out sqw wdi pfi rst pfo v bat xi xo
description M41ST84W 8/34 figure 2. 16-pin soic connections figure 3. block diagram 1. open drain output ai03678 8 2 3 4 5 6 7 9 10 11 12 13 14 16 15 1 rstin wdi irq/ft/out sda v bat pfi nc sqw scl nc pfo v ss rst xo xi v cc M41ST84W ai03931 compare v pfd = 2.65v v cc compare v so = 2.5v v int v bl = 2.5v bl compare crystal 400khz i 2 c interface real time clock calendar 44 bytes user ram rtc w/alarm & calibration watchdog square wave sda scl 1.25v pfi pfo rstin por sqw rst (1) wdi wdf af irq/ft/out (1) v bat 32khz oscillator compare (internal) v ss xi xo
M41ST84W description 9/34 figure 4. hardware hookup 1. user-supplied crystal ai03680 v cc pfo scl wdi rstin pfi v ss v bat irq/ft/out sqw rst sda xo xi M41ST84W unregulated voltage regulator v cc v in to rst to led display to nmi to int r1 32khz (1) xtal r2 from mcu
operating modes M41ST84W 10/34 2 operating modes the M41ST84W clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 64 bytes contained in the device can then be accessed sequentially in the following order: 1. tenths/hundredths of a second register 2. seconds register 3. minutes register 4. century/hours register 5. day register 6. date register 7. month register 8. year register 9. control register 10. watchdog register 11. - 16. alarm registers 17. - 19. reserved 20. square wave register 21. - 64. user ram the M41ST84W clock continually monitors v cc for an out-of tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the de vice will not be recognized at th is time to prevent erroneous data from being written to the device from a an out-of-tolerance system. when v cc falls below v so , the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conser ve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). for more information on battery storage life refer to application note an1012. 2.1 2-wire bus characteristics the bus is intended for communication between di fferent ics. it consists of two lines: a bi- directional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock lin e is high, will be interpreted as control signals.
M41ST84W operating modes 11/34 accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high. 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. 2.1.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter?, the receiving device that gets the message is called ?receiver?. th e device that controls the message is called ?master?. the devices that are controlled by the master are called ?slaves?. 2.1.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition.
operating modes M41ST84W 12/34 figure 5. serial bus data transfer sequence figure 6. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 msb lsb
M41ST84W operating modes 13/34 figure 7. bus timing requirements sequence table 2. ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6 v (except where noted). min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t f sda and scl fall time 300 ns t hd:dat (2) 2. transmitter must internally provide a hold time to bridge the undefined region ( 300 ns max) of the falling edge of scl. data hold time 0 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
operating modes M41ST84W 14/34 2.2 read mode in this mode the master reads the M41ST84W slave after setting the slave address (see figure 8 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address ?an? is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter becomes th e master receiver. the data by te which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the M41ST84W slave transmitter will now place the da ta byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter (see figure 9 on page 15 ). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei ther due to a stop condition or when the pointer increments to a non-clock or ram address. note: this is true both in read mode and write mode. an alternate read mode may also be implemented whereby the master reads the M41ST84W slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 10 on page 15 ). figure 8. slave address location ai00602 r/w slave address start a 01000 11 msb lsb
M41ST84W operating modes 15/34 figure 9. read mode sequence figure 10. alternate read mode sequence ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n + 1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n + 1 data n + x slave address
operating modes M41ST84W 16/34 2.3 write mode in this mode the master transmitter transmits to the M41ST84W slave receiver. bus protocol is shown in figure 11 . following the start condition and slave address, a logic '0' (r/w =0) is placed on the bus and indica tes to the addressed device t hat word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the M41ST84W slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address (see figure 8 on page 14 ) and again after it has received the word address and each data byte. 2.4 data retention mode with valid v cc applied, the M41ST84W can be accessed as described above with read or write cycles. should the supply voltage deca y, the M41ST84W will automatically deselect, write protecting itself when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally inhibiting access to the clock registers. at this time, the reset pin (rst ) is driven active and will remain active until v cc returns to nominal levels. when v cc falls below the battery backup switchover voltage (v so ), power input is switched from the v cc pin to the external battery, and the clock registers and sram are maintained from the attached battery supply. all outputs become high impedance. on power up, when v cc returns to a nominal value, write protection continues for t rec . the rst signal also remains active during this time (see figure 18 on page 30 ). for a further more detailed review of lifetime calculations, please see application note an1012. figure 11. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n + 1 data n + x word address (an) slave address
M41ST84W clock operation 17/34 3 clock operation the eight byte clock register (see table 3 on page 18 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to ?00,? and tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d6 and d7 of clock register 03h (century/hours register) contain the century enable bit (ceb) and the century bit (cb). se tting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01 h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stop ped to reduce current drain. when reset to a '0' the oscillator restarts within one second. the eight clock registers may be read one byte at a time, or in a sequential block. the control register (address location 08h) may be accessed independently. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock addr ess is being read, an update of the clock registers will be halted. this will prevent a transit ion of data during the read. 3.1 power-down time-stamp when a power failure occurs, the halt update bi t (ht) will automatically be set to a '1.' this will prevent the clock from updating the timekeeper ? registers, and will allow the user to read the exact time of the powe r-down event. resetting the ht bi t to a '0' will allow the clock to update the timekeeper registers with the current time. for more information, see application note an1572. 3.2 timekeeper ? registers the M41ST84W offers 12 additional internal registers which contain the alarm, watchdog, flag, square wave and control data. these registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are ind ependent of inte rnal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the internal divider (or clock) chain will be re set upon the completion of a write to any clock address. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei ther due to a stop condition or when the pointer increments to a non-clock or ram address. timekeeper and alarm registers store data in bcd. control, watchd og and square wave registers store data in binary format.
clock operation M41ST84W 18/34 table 3. timekeeper ? register map address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24 hour format) century/hours 0-1/00-23 04h tr 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 bl 0 0 0 0 flags 10h00000000reserved 11h00000000reserved 12h00000000reserved 13h rs3 rs2 rs1 rs0 0 0 0 0 sqw keys: s = sign bit rb0-rb1 = watchdog resolution bits ft = frequency test bit wds = watchdog steering bit st = stop bit abe = alarm in battery backup mode enable bit 0 = must be set to zero rpt1-rpt5 = alarm repeat mode bits bl = battery low flag (read only) wdf = watchdog flag (read only) bmb0-bmb4 = watchdog multiplier bits af = alarm flag (read only) ceb = century enable bit sqwe = square wave enable cb = century bit rs0-rs3 = sqw frequency out = output level ht = halt update bit afe = alarm flag enable flag tr = t rec bit
M41ST84W clock operation 19/34 3.3 calibrating the clock the M41ST84W is driven by a quartz controlled oscillator wi th a nominal frequency of 32,768 hz. the devices are te sted not exceed +/?35 ppm (p arts per million) oscillator frequency error at 25 o c, which equates to about +/?1.53 minutes per month. when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals changes with temperature (see figure 12 on page 20 ). therefore, the M41ST84W design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscilla tor divider circuit at th e divide by 256 stage, as shown in figure 13 on page 20 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register (08h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 1 28 or lengthened by 2 56 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. as suming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given M41ST84W may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934: timekeeper calibration. this allows the designer to gi ve the end user the ability to calibrate the clock as the environm ent requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of the irq /ft/out pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 01h) is '0,' the frequency test bit (ft, d6 of 08h) is '1,' the alarm flag enable bit (afe, d7 of 0ah) is '0,' and the watchdog steering bit (wds, d7 of 09h) is '1' or the watchdog register (09h = 0) is reset. any deviation from 512 hz indicates the degree and direction of oscilla tor frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscillator frequency erro r, requiring a ?10 (xx001010) to be loaded into the ca libration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. the irq /ft/out pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500 to 10 k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down.
clock operation M41ST84W 20/34 figure 12. crystal accuracy across temperature figure 13. clock calibration 3.4 setting alarm clock registers address locations 0ah-0eh contain the alarm settings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. it can also be programmed to go off while the M41ST84W is in the battery backu p to serve as a system wakeup call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. ta b l e 4 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. ai00999b ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = k x (t ?t o ) 2 k = ?0.036 ppm/ c 2 0.006 ppm/ c 2 t o = 25 c 5 c f ai00594b normal positive calibration negative calibration
M41ST84W clock operation 21/34 when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condition activates the irq /ft/out pin. note: if the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address poin ter is moved to a different address. it should also be noted that if the last address written is the ?alarm seconds,? the address pointer will incr ement to the flag address, ca using this situation to occur. the irq /ft/out output is cleared by a read to the flags register as shown in figure 14 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /ft/out pin can also be activated in the battery backup mode. the irq /ft/out will go low if an alarm occurs and both abe (ala rm in battery backup mode enable) and afe are set. the abe and afe bits are reset during power-up, th erefore an alarm generated during power-up will only set af. the user can read the flag register at system boot-up to determine if an alarm was generated while the M41ST84W was in the deselect mode during power-up. figure 15 on page 22 illustrates the backup mode alarm timing. figure 14. alarm interrupt reset waveform table 4. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111once per second 11110once per minute 11100once per hour 11000once per day 10000once per month 00000once per year ai03664 irq/ft/out active flag 0fh 0eh 10h high-z
clock operation M41ST84W 22/34 figure 15. backup mode alarm waveform 3.5 watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five-bit multiplier valu e with the resolution. (for example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). note: accuracy of timer is withi n the selected resolution. if the processor does not reset the timer within the specified period, the M41ST84W sets the wdf (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0,' the watchdog will activate the irq /ft/out pin when timed-out. when wds is set to a '1,' the watchdog will outp ut a negative pulse on the rst pin for t rec . the watchdog register, ft, afe, abe and sqwe bits will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi) or 2) the microprocessor can perform a write of the watchdog register. the time-out period then starts over. note: the wdi pin should be tied to v ss if not used. in order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the irq /ft/out ai03920 v cc irq/ft/out v pfd abe, afe bits in interrupt register af bit in flags register high-z v so high-z trec
M41ST84W clock operation 23/34 pin. this will also disable the watchdog functi on until it is again programmed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft/out pin and the frequency test (ft) function is activated, the watchdog function prevails and the frequency test function is denied. 3.6 square wave output the M41ST84W offers the user a programmable square wave function which is output on the sqw pin. the rs3-rs0 bits located in 13h establish the square wave output frequency. these frequencies are listed in ta b l e 5 . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. table 5. square wave output frequency 3.7 power-on reset the M41ST84W continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time. square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 000132.768khz 0 0 1 0 8.192 khz 0 0 1 1 4.096 khz 0 1 0 0 2.048 khz 0 1 0 1 1.024 khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
clock operation M41ST84W 24/34 3.8 reset input (rstin ) the M41ST84W provides an independent input which can generate an output reset. the duration and function of this reset is identical to a reset generated by a power cycle. ta b l e 6 and figure 16 illustrate the ac reset characteristics of this function. pulses shorter than t rlrh will not generate a reset condition. rstin is internally pulled up to v cc through a 100 k resistor. figure 16. rstin timing waveform note: with pull-up resistor table 6. reset ac characteristics 3.9 power-fail input/output the power-fail input (pfi) is compared to an internal reference voltage (1.25 v). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo) will go low. this function is intended for use as an under-vol tage detector to signal a failin g power supply. typically pfi is connected through an external voltage divider (see figure 4 on page 9 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several milliseconds before the regulated v cc input to the M41ST84W or the microprocessor drops below the minimum operating voltage. during battery backup, the power-fail comparator turns off and pfo goes (or remains) low. this occurs after v cc drops below v pfd (min). when power returns, pfo is forced high, irrespective of v pfi for the write protect time (t rec ), which is the time from v pfd (max) until the inputs are recognized. at the end of this time, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. ai03682 rst (1) rstin trlrh trhrsh symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6 v (except where noted). min max unit t rlrh (2) 2. pulse width less than 50 ns will result in no reset (for noise immunity). rstin low to rstin high 200 ns t rhrsh (3) 3. programmable (see table 8 on page 26 ) rstin high to rst high 40 200 ms
M41ST84W clock operation 25/34 3.10 century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a ?1? will cause cb to toggle, either from a ?0? to ?1? or from ?1? to ?0? at the turn of the century (depending upon its initial state). if ceb is set to a ?0?, cb will not toggle. 3.11 output driver pin when the ft bit, afe bit and watchdog register are not set, the irq /ft/out pin becomes an output driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) and d6 (ft bit) of address location 08h are a '0,' then the irq /ft/out pin will be driven low. note: the irq /ft/out pin is an open drain which requires an external pull-up resistor. 3.12 battery low warning the M41ST84W automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be asserted if the battery volt age is found to be less than approximately 2.5 v. the bl bit will remain asse rted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. however, data is not compromised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery backup mode, the battery should be replaced. the battery may be replaced while v cc is applied to the device. the M41ST84W only monitors the battery when a nominal v cc is applied to the device. thus applications which require extensive dura tions in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 3.13 t rec bit bit d7 of clock register 04h contains the t rec bit (tr). t rec refers to the automatic continuation of the deselect time after v cc reaches v pfd . this allows for a voltage setting time before writes may again be performed to the device after a power-down condition. the t rec bit will allow the user to set the length of this deselect time as defined by table 7 on page 26 .
clock operation M41ST84W 26/34 3.14 initial power-on defaults upon initial application of power to the device, the following register bits are set to a '0' state: watchdog register, tr, ft, afe, abe, and sqwe. the following bi ts are set to a '1' state: st, out, and ht (see table 8 on page 26 ). table 7. t rec definitions table 8. default values t rec bit (tr) stop bit (st) t rec time units min max 0 0 96 98 ms 0 1 40 200 (1) 1. default setting ms 1 x 50 2000 s condition tr st ht out ft afe abe sqwe watchdog register (1) 1. wds, bmb0-bmb4, rb0, rb1. initial power-up (battery attach) (2) 2. state of other control bits undefined. 0111000 0 0 subsequent power-up (with battery backup) (3) 3. uc = unchanged uc uc 1 uc 0 0 0 0 0
M41ST84W maximum ratings 27/34 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 9. absolute maximum ratings caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. symbol parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 150 c t sld (1)(2) 1. for so package, standard (snpb) lead finish: reflow at peak temperat ure of 225c (total thermal budget not to exceed 180c for between 90 to 150 seconds). 2. for so package, lead-free (p b-free) lead finish: reflow at peak temp erature of 260c (total thermal budget not to exceed 245c for greater than 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to v cc + 0.3 v v cc supply voltage ?0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
dc and ac parameters M41ST84W 28/34 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 10. dc and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 17. ac testing input/output waveforms note: 50 pf for M41ST84W. table 11. capacitance parameter M41ST84W v cc supply voltage 2.7 to 3.6 v ambient operating temperature ?40 to 85c load capacitance (c l ) 50 pf input rise and fall times 50 ns input pulse voltages 0.2 to 0.8v cc input and output timing ref. voltages 0.3 to 0.7v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1)(2) 1. effective capacitance measured with power supply at 3 v. sampled only, not 100% tested. 2. at 25c, f = 1 mhz. min max unit c in input capacitance 7 pf c io (3) 3. outputs deselected. input / output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
M41ST84W dc and ac parameters 29/34 table 12. dc characteristics table 13. crystal electrical characteristics (externally supplied) sym parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6 v (except where noted). M41ST84W unit min typ max i bat battery current osc on t a = 25c, v cc = 0 v, v bat = 3 v 400 500 na battery current osc off 50 na i cc1 supply current f = 400 khz 0.75 ma i cc2 supply current (standby) scl, sda = v cc ? 0.3 v or v ss + 0.3 v 0.50 ma i li (2) 2. rstin internally pulled-up to v cc through 100 k resistor. wdi internally pulled-down to v ss through 100 k resistor. input leakage current 0v v in v cc 1 a input leakage current (pfi) ?25 2 25 na i lo (3) 3. outputs deselected. output leakage current 0v v out v cc 1 a v ih input high voltage 0.7v cc v cc + 0.3 v v il input low voltage ?0.3 0.3v cc v v bat battery voltage 2.5 3.0 3.5 (4) 4. for rechargeable backup, v bat (max) may be considered v cc . v v oh output high voltage (5) 5. for pfo and sqw pins (cmos). i oh = ?1.0ma 2.4 v v ol output low voltage i ol = 3.0ma 0.4 v output low voltage (open drain) (6) 6. for irq /ft/out, rst pins (open drain): if pull ed-up to supply other than v cc , this supply must be equal to, or less than 3.0 v when v cc = 0 v (during battery backup mode). i ol = 10ma 0.4 v pull-up supply voltage (open drain) rst , irq /ft/out 3.6 v v pfd power fail deselect 2.55 2.60 2.70 v v pfi pfi input threshold v cc = 3v(w) 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 mv v so battery backup switchover 2.5 v symbol parameter (1)(2) 1. load capacitors are integrated within the M41ST84W. circuit board layout consi derations for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account. 2. stmicroelectronics recommends the kds dt-38: 1ta/1tc 252e127, tuning fork type (t hru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crys tal for industrial temperature operations. kds can be contacted at http://www.kds.info/index_en.htm for further information on this crystal type. typ min max unit f 0 resonant frequency 32.768 khz r s series resistance 50 k c l load capacitance 12.5 pf
dc and ac parameters M41ST84W 30/34 figure 18. power down/up mode ac waveforms table 14. power down/up ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6 v (except where noted). min typ max unit t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write prot ection not occurring until 200 s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time 10 s t pfd pfi to pfo propagation delay 15 25 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1 s t rec (4) 4. programmable (see table 7 on page 26 ) power up deselect time 40 200 ms ai03681 v cc inputs (per control input) outputs don't care high-z tf tfb tr trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec rst pfo
M41ST84W package mechanical data 31/34 6 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications ar e available at www.st.com. figure 19. so16 ? 16-lead plastic small outline, package outline note: drawing is not to scale. table 15. so16 ? 16-lead plastic small outline, package mechanical data so-b e n cp b e a2 d c l a1 h a 1 symbol mm inches typ. min. max. typ. min. max. a 1.75 0.069 a1 0.10 0.25 0.004 0.010 a2 1.60 0.063 b 0.35 0.46 0.014 0.018 c 0.19 0.25 0.007 0.010 d 9.80 10.00 0.386 0.394 e 3.80 4.00 0.150 0.158 e1.27? ?0.050? ? h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 a 08 08 n16 16 cp 0.10 0.004
part numbering M41ST84W 32/34 7 part numbering table 16. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41st 84w mq 6 e device type m41st supply voltage and write protect voltage 84w = v cc = 2.7 to 3.6 v; 2.55 v v pfd 2.70 v package mq = so16 temperature range 6 = ?40 to 85c shipping method for so16: e = ecopack ? package, tubes f = ecopack ? package, tape & reel
M41ST84W revision history 33/34 8 revision history table 17. document revision history date revision changes aug-2000 1 first issue 24-aug-2000 1.2 block diagram added ( figure 3 ) 08-sep-2000 1.3 so16 package measures change 18-dec-2000 2 reformatted, toc added, and pfi input leakage current added ( ta bl e 1 2 ) 18-jun-2001 2.1 addition of t rec information, table changed, one added ( ta bl e 3 , 7 ); changes to pfi/pfo graphic (see figure 3 ); change to dc and ac characteristics, order information ( ta b l e 1 2 , 2 , 16 ); note added to ?setting alarm clock registers? section; added temp./voltage info. to tables ( ta b l e 1 1 , 12 , 13 , 2 , 14 ); addition of default values ( ta b l e 8 ); textual improvements 25-jun-2001 2.2 special note added in section 3: clock operation on page 17 26-jul20-01 3 change in product maturity 07-aug-2001 3.1 improve text for ?setting the alarm clock? section 20-aug-2001 3.2 change v pfd values in document 06-sep-2001 3.3 dc characteristics v bat changed; pfi hysteresis (pfi rising) spec. added; and crystal electrical characteristics series resistance spec. changed ( ta b l e 1 2 , 13 ) 03-dec-2001 3.4 change read/write mode sequence drawings ( figure 9 , 11 ); change in v pfd lower limit for 5v (m41st84y) part only ( ta bl e 1 2 , 16 ) 14-jan-2002 3.5 change series resistance ( ta b l e 1 3 ) 01-may-2002 3.6 change t rec definition ( ta bl e 7 ); modify reflow time and temperature footnote ( ta b l e 9 ) 03-jul-2002 3.7 modify dc and crystal electrical characteristics footnotes, default values ( ta b l e 1 2 , 13 , 8 ) 01-aug-2002 3.8 add marketing status ( figure 1 ; ta b l e 1 6 ) 16-jun-2003 4 new si changes ( ta b l e 1 4 , 6 , 7 , 8 ) 15-jun-2004 5 reformatted; added lead-free inform ation; update characteristics ( figure 12 ; ta bl e 9 , 12 , 16 ) 18-oct-2004 6 add marketing status ( figure 1 ; ta b l e 1 6 ) 10-jan-2006 7 updated template, lead-free text, characteristics ( figure 1 , 2 , 5 , 6 ; ta b l e 1 , 2 , 6 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 16 ) 28-aug-2008 8 reformatted document and modified title; updated cover page, figure 3 , ta bl e 1 3 , 16 , and section 6: package mechanical data .
M41ST84W 34/34 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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